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? semiconductor components industries, llc, 2016 april, 2018 ? rev. 3 1 publication order number: FUSB307B/d FUSB307B usb type-c port controller with usb-pd description the FUSB307B targets system designers looking to implement up to four usb type?c port controllers (tcpc) with usb?pd capabilities. this solution provides integrated type?c rev 1.3 detection circuitry enabling manual attach/detach detection. time critical power delivery functionality is handled autonomously, offloading the processor or t ype?c port manager (tcpm). the FUSB307B complies with the usb?pd interface specification rev 1.0 as a tcpc for a standardized interface with tcpm. features ? usb?pd interface specification rev 1.0 ver. 1.2 compatible ? usb type?c rev 1.3 compatible ? usb?pd rev3.0 ver. 1.1 compatible ? fast role swap ? sink transmit ? extended data messages (chunked) ? dual?role functionality ? manual t ype?c detection ? automatic drp toggling ? usb?pd interface specification support ? automatic goodcrc packet response ? automatic retries of sending packet ? all sop* types supported ? vbus source and sink control ? integrated 3 w capable vconn to ccx switch ? 10?bit vbus adc ? programmable gpios ? 4 selectable i 2 c addresses figure 1. FUSB307B block diagram www. onsemi.com scale 3:1 wqfn16 3 x 3, 0.5p case 510bs ordering information 8 dbg_n gnd 4 orient 3 cc2 2 vconn 1 cc1 9 gpio2 10 int_n 11 scl1 12 sda1 7 vdd 6 vbus 5 ldo 13 src 14 snk 15 gnd 16 gpio1 top through view qfn16 see detailed ordering and shipping information on page 3 o f this data sheet. f eatures (continued) ? dead battery operation ? powered from vbus ? ldo output provides power to tcpm ? packaging: ? FUSB307B? 16 pin qfn a pplications ? smartphones and tablets ? digital cameras ? desktops and laptops ? rechargeable docks/speakers ? wall adapters ? automotive pin assignment
FUSB307B www. onsemi.com 2 table of contents description 1 ............................................................................................. features 1 ................................................................................................ applications 1 ............................................................................................. typical application 3 ....................................................................................... block diagram 4 .......................................................................................... pin configurations 4 ....................................................................................... pin descriptions 5 ......................................................................................... power up, initialization and reset 5 .......................................................................... dead battery power?up 6 .................................................................................. programmable gpiox 6 .................................................................................... standard outputs 6 ........................................................................................ i 2 c interface 7 ............................................................................................ i 2 c address selection 7 .................................................................................... interrupt operation 7 ....................................................................................... i 2 c idle mode 7 ........................................................................................... vconn control 7 ......................................................................................... debug accessory support 8 ................................................................................ type?c manual mode detection 8 ........................................................................... bmc power delivery 10 .................................................................................... transmit state machine 11 .................................................................................. hard reset/ cable reset state machine 12 ................................................................... automatic goodcrc response 12 .......................................................................... bist mode 12 ............................................................................................ vbus source and sink control 12 ........................................................................... voltage transitions 13 ...................................................................................... vbus monitoring and measurement 15 ....................................................................... vbus discharge 15 ....................................................................................... automatic source discharge after a disconnect 15 ............................................................. automatic sink discharge after a disconnect 16 ............................................................... sink discharge during a connection 17 ....................................................................... watchdog timer 17 ........................................................................................ usb?pd rev 3.0 features 18 ............................................................................... fast role swap 18 ........................................................................................ fast role swap cable disconnect (informational only) 19 ...................................................... dc and transient characteristics 21 .........................................................................
FUSB307B www. onsemi.com 3 table 1. ordering information part number operating temperature range package packing method ? FUSB307Bmpx ?40 to 85 c 16?lead molded leadless package (qfn) jedec, ml220, 3 mm square tape and reel FUSB307Bvmpx automotive ?40 to 105 c ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. typical application figure 2. FUSB307B typical mobile computing application cc2 cc1 int_n sda scl type?c receptacle FUSB307B gnd vconn vdd vbus tcpm usb 2.0 & 3.1 gen1 phy usb buck/boost charger + vbus buck + vconn buck battery snk vbat v3p3 vconn vsnk vsrc fpf2895 src i2c_addr_sel/ orient gpo1 gpu ldo vdd fpf2895 en fusb340 2:1 usb3.1 switch gpo2 debug_n 30 m v out v in iset on 1 f 25 v 30 m v in v out 10 f 10 f 25 v 1 f 10 f 1 f 220 pf 220 pf
FUSB307B www. onsemi.com 4 block diagram figure 3. FUSB307B block diagram usb pd phy bmc driver bmc rcvr cc switch/ sense clock gen. vdd int_n sda1/scl2 scl1/sda2 cc1 cc2 vconn vbus prog pull? up current type?c control cdr crc32 tx crc32 rx 4b5b bmc enc. bmc dec. FUSB307B addr/ orient usb pd fsm discharge bleed discharge discharge gpio control pwr mgmt snk src gpio2/ fr_swap sink/source control debug_n gnd gpio1 3.3v ldo ldo 4b5b 10?bit adc i2c pin configurations figure 4. pin assignment qfn (FUSB307B) gnd 8 dbg_n gnd 4 orient 3 cc2 2 vconn 1 cc1 9 gpio2 10 int_n 11 scl1 12 sda1 7 vdd 6 vbus 5 ldo 13 src 14 snk 15 gnd 16 gpio1 bottom view top through view 4 orient 3 cc2 2 vconn 1 cc1 9 gpio2 10 int_n 11 scl1 12 sda1 8 dbg_n 7 vdd 6 vbus 5 ldo 13 src 14 snk 15 gnd 16 gpio1
FUSB307B www. onsemi.com 5 pin descriptions table 2. pin description name type description usb type?c connector interface cc1 i/o type?c connector configuration channel (cc) pins. initially used to determine when an attach has occurred and what the orientation of the insertion is. function - ality after attach depends on mode of operation detected. operating as a host: ? sets the allowable charging current for vbus to be sensed by the attached device ? used to communicate with devices using usb bmc power delivery ? used to detect when a detach has occurred operating as a device: ? indicates what the allowable sink current is from the attached host ? used to communicate with devices using usb bmc power delivery cc2 i/o gnd ground ground vbus power vbus supply pin for attach and detach detection when operating as an upstream facing port (device) power interface vdd power input supply voltage ldo ldo output 3.3 v ldo output vconn power switch regulated input to be switched to correct cc pin as vconn to power usb3.1 fully featured cables, powered accessories or dongles bridging type c to other video or audio connectors signal interface scl1/sda2 (note 1) open?drain i/o i 2 c serial clock/data signal to be connected to the i 2 c master sda1/scl2 (note 1) open?drain i/o i 2 c serial clock/data signal to be connected to the i 2 c master int_n open?drain output active low open drain interrupt output used to prompt the processor to read the i 2 c register bits orient/i2c_ addr (note 1) 3?state cmos output selects i 2 c address on power up and then becomes a general purpose cmos output dbg_n open?drain i/o debug accessory detection open?drain output gpio2 3?state cmos i/o general purpose i/o 2 gpio1 3?state cmos i/o general purpose i/o 1 vbus source and sink interface snk cmos output controls external vbus sink load switch on/off (active high) src cmos output controls external vbus source load switch on/off (active high) 1. a different i2c address is used depending on which sda and scl are used and the state of orient/i2c_addr at power up. power up, initialization and reset when power is first applied to vdd or vbus, the FUSB307B goes through its por sequence to load up all the default values in the register map, read all the fuses so that the trimmed values are available when vdd or vbus is in its valid range. a software reset can be executed by writing sw_res to 1 in reset register . this executes a full reset of the FUSB307B similar to por where all the i2c registers go to their default state. when powered down, the FUSB307B is configured as a ufp with cc1 and cc2 have their respective rd pull?downs enabled such that a source can detect this as a ufp and turn on vbus. for the FUSB307B device, power may become available from vbus when vdd is not present. this state is still considered ?dead battery? until vdd is present. during dead battery, the FUSB307B will continue presenting rd. once vdd is available, the tcpm can start the drp toggle by setting command.look4con on the FUSB307B device.
FUSB307B www. onsemi.com 6 dead battery power?up during a dead battery condition in a mobile application, the FUSB307B will be powered by vbus and provide an ldo output to power a controller or tcpm to establish a usb?pd contract. the FUSB307B will enable the sink path when attached to a source with any advertised current. systems with more than one type?c port, the tcpm can enable or disable the appropriate sink paths. once vdd is greater than v ddgood , the internal ldo is bypassed and the device switches from vbus to vdd power. figure 5 demonstrates a dead battery power up sequence for FUSB307B. figure 5. FUSB307B dead battery operation vdd vbus FUSB307B pwr mgmt 3.3v ldo ldo ldo bypass snk charger ic tcpm ec vdd vin vbus FUSB307B pwr mgmt 3.3 v ldo ldo ldo bypass snk vdd 3.3 v buck converter vsys v3p3a type?c port 1 type?c port 2 fpf2895 en fpf2895 en 2 ? FUSB307B provides power to ec during dead battery 5 ? power to system is enabled 1 ? FUSB307B powers from vbus and attaches as snk 3 ? enable sink path 4 ? tcpm establishes pd contract with src battery 30 m v out v in v out v in 30 m 6 ? FUSB307B switches to vdd power and bypasses ldo programmable gpiox the FUSB307B has two programmable gpios. these can be programmed to be inputs, cmos outputs or open drain outputs. to configure them, the tcpm writes to gpio1_cfg and gpio2_cfg. if the gpio is configured as an input, its logic value can be read in gpio_stat and alert_vd registers. standard outputs the FUSB307B implements orientation and supports debug accessory detection output as indicated in std_out_cap register. to configure the orientation, mux selection, and debug accessory, the tcpm writes to std_out_cfg.
FUSB307B www. onsemi.com 7 i 2 c interface the FUSB307B includes a full i 2 c slave controller. the i2c slave fully complies with the i2c specification version 6 requirements. this block is designed for fast mode plus signals. examples of an i 2 c write and read sequence are shown in figure 7 and figure 8 respectively. s wr a aa a a a p note: single byte read is initiated by master with p immediately following first data byte. 8bits 8bits 8bits write data k+2 slave address register address k write data write data k+1 write data k+n?1 s wr a a s rd a a a na p register address to read specified 8bits note: if register is not specified master will begin read from current register. in this case only sequence showing in red bracket is needed. single or multi byte read executed from current register location (single byte read is initiated by master with na immediately following first data byte) read data k+1 read data k+n?1 8bits 8bits 8bits slave address register address k read data k slave address from master to slave s start condition na not acknowledge (sda high) rd read =1 from slave to master a acknowledge (sda low) wr write = 0 p stop condition figure 6. i2c write example figure 7. i2c read example i 2 c address selection i2c slave addresses can be changed by configuring the i2c_addr_gpo input on power up with a pull?up or pull?down resistor and routing the scl and sda lines according to table 3. interrupt operation the int_n pin is an active low, open drain output which indicates to the host processor that an interrupt has occurred in the FUSB307B which needs attention. the int_n pin is asserted after power?up or device reset reset.sw_res set to 1b (due to alertl.i_port_pwr and pwrstat.tcpc_init). when an interruptible event occurs, int_n is driven low and is high?z again when the processor clears the interrupt by writing a 1 to the corresponding interrupt bit position. writing a 0 to an interrupt bit has no effect. a processor firmware has additional control of int_n through individual event mask bits which can be set or cleared to enable or disable int_n from being driven low when each event occurs. table 3. i 2 c addresses i2c_addr sclx/sdax slave address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0 scl1/sda1 1 0 1 0 0 0 0 r/w 1 scl1/sda1 1 0 1 0 0 0 1 r/w 0 scl2/sda2 1 0 1 0 0 1 0 r/w 1 scl2/sda2 1 0 1 0 0 1 1 r/w i 2 c idle mode entering i 2 c idle mode the FUSB307B does not need to enter i 2 c idle mode in order to save power. entering this mode has no effect on i 2 c function. the FUSB307B can enter idle mode if 0xff is written to the command register. once in idle mode, the FUSB307B will not set the pwrstat.tcpc_init to one. exiting i 2 c idle mode the FUSB307B will exit i 2 c idle mode when any i 2 c communication is addressed to the slave. the alertl.i_prt_pwr interrupt will be set and no pwrstat bits will be set. the device?s i 2 c block is always on without power penalties.
FUSB307B www. onsemi.com 8 vconn control the FUSB307B integrates a ccx to vconn switch with programmable ocp capability via the vconn_ocp register. if pwrctrl.vconn_pwr is set to 0, the standard vconn current limit is used (210.5 ma). if pwrctrl.vconn_pwr is set to 1, the programmable vconn_ocp is used. the vconn switch can be enabled via the pwrctrl register bits en_vconn and tcpc_ctrl.orient bits (for cc1/2 selection). a vconn valid voltage is monitored and reported on pwrstat.vconn_val. the valid voltage threshold is fixed at 2.4 v. debug accessory support the FUSB307B implements autonomous detection of source and sink debug accessories. a debug accessory detection is indicated via a standard output. the FUSB307B powers on looking for a debug accessories without processor intervention. if debug accessory detection is not wanted, the processor can write tcpc_ctrl.debug_acc_ctrl = 1b. type?c manual mode detection the cc pull up (rp) or pull down (rd) resistors and drp toggle are setup via the rolectrl register.if a tcpm wishes to control rp/rd directly, it can write rolectrl.drp = 0b and the desired rolectrl bits [3:0] (cc1/cc2). the FUSB307B can autonomously toggle the rp/rd by setting rolectrl.drp = 1b and the starting value of rp/rd in rolectrl.bits [3:0]. drp toggling starts by writing to the command register if rolectrl.drp = 1b, the only allowed values for cc1/cc2 in rolectrl bits [3:0] are rp/rp or rd/rd. when rolectrl bits 3:0 are set to open and rolectrl.drp = 0b, the phy and cc comparators are powered down. the FUSB307B updates the ccstat register on a connect, disconnect, a change in rolectrl.drp or a change (ttcpcfilter debounced) on the cc1 or cc2 wire. the tcpm reads ccstat upon detecting an interrupt and seeing the alertl.i_ccstat = 1. the FUSB307B indicates the drp status, the drp result, and the current cc status in this register. the FUSB307B will set ccstat.look4con = 0b when it has stopped toggling as a drp. the tcpm reads the ccstat .look4con to determine if the FUSB307B is toggling rp/rd when operating as a drp, it then reads ccstat.con_res to determine if the FUSB307B is presenting an rp or rd and read the ccstat.cc1_stat and ccstat.cc2_stat to determine the cc1 and cc2 states. the FUSB307B debounces the cc lines for ttcpcfilter before reporting the status on ccstat. the tcpm must complete the debounce as defined in type?c specification.
FUSB307B www. onsemi.com 9 figure 8. drp initialization and connection detection set fusb305b to drp write: rolectrl.drp = 1b rolectrl.cc2 = 01b or 10b rolectrl.cc1 = 01b or10b rolectrl.cc1 = rolectrl.cc2 pwrctrl.auto_disch = 0b command.look4con no connection monitor for alert alert.ccstat = 1b? drp toggling set ccstat.look4con = 1b drptoggleflag = 1b start drp toggling monitor for a connection potential connect as source either cc = src.rd or both cc = src.ra for > ttcpcfilter potential connect as sink either cc != snk.open for > ttcpcfilter set source status ccstat.look4con = 0b ccstat.con_res = 0b stop toggling rp/rd apply rp set sink status ccstat.look4con = 0b ccstat.con_res = 1b stop toggling rp/rd apply rd interrupt set alert.ccstat = 1b read alert service other alerts read ccstat ccstat.look4con = 0b? debounce cc status read ccstat and debounce for tccdebounce determine cc & vconn write: rolectrl.cc1 & cc2 per decision set pwrctrl.auto_disch tcpc_ctrl.orient pwrctrl.en_vconn clear alert.ccstat connection established monitor for alert monitor for a disconnect no yes yes no FUSB307B tcpm connection enable vbus and vconn write command to source/sink vbus per decision check pwrstat.vbus_val = 1b check pwrstat.vconn_val = 1b
FUSB307B www. onsemi.com 10 bmc power delivery the type?c connector allows usb power delivery (pd) to be communicated over the connected cc pin between two ports. the communication method is the bmc power delivery protocol and is used for many different reasons with the t ype?c connector. possible uses are outlined below. ? negotiating and controlling charging power levels ? alternative interfaces such as mhl, display port ? vendor specific interfaces for use with custom docks or accessories ? role swap for dual?role ports that want to switch who is the host or device ? communication with usb3.1 full featured cables the FUSB307B integrates a thin bmc pd client which includes the bmc physical layer and packet buffers which allows packets to be sent and received by the host software through i 2 c accesses. receive state machine the tcpm can setup the desired types of messages to be received by the FUSB307B via the rxdetect register. this register defaults to 0x00 (receiver disabled) upon power up, reset, hard reset transmission and reception, and upon detecting a cable disconnect. a message is not received unless it is first enabled. figure 9 shows the FUSB307B receive state machine. upon a successfully transmitting goodcrc, the rxstat register is updated with the type of message received and the tcpm is alerted via aler tl.i_rxstat bit (see transition from prl_rx_send_goodcrc to prl_rx_report_sop* in figure 9). the total number of bytes in the receive buffer rxdata is stored in rxbytecnt this number includes the header bytes that are stored in rxheadl and rxheadh and the rxstat register. the rxbytecnt, rxstat registers and the internal receive buf fer will be cleared after the aler tl.i_rxstat bit is cleared. the FUSB307B will automatically transmit a goodcrc message for valid enabled messages within ttransmit. a received message is valid when: ? it is not a goodcrc message ? the calculated crc is correct ? the sop* type is enabled the makeup of the goodcrc message is formed by the received sop* type and the contents of msgheadr register. when an expected goodcrc message or a hard reset signaling is received, they will not be replied with a goodcrc message (see note 2 in figure 9). if a goodcrc message received was not expected due to the sop* type or mismatched message id, the receive state machine will not send a goodcrc message and will transition to prl_rx_report sop* to inform the tcpm. if a hard reset message is received, the FUSB307B will reset the rxdetect preventing the reception of future messages until the tcpm re?enables it. figure 9. receive state machine message received from phy goodcrc transmission complete start prl_rx_send_goodcrc actions on entry: send goodcrc message to phy prl_rx_wait_for_phy_ message actions on entry: prl_rx_report_sop* actions on entry: update receive_status (alert_l.rxstat asserted) message discarded bus idle prl_rx_message_discard actions on entry: if tx state?machine active, discard transmission and assert alert_l.txdisc else unexpected goodcrc received fusb305 receives hard reset | cable reset 1. this indication is sent by the phy when a message has been discarded due to cc being busy, and after cc becomes idle again (see usb pd spec). 2. messages do not include hard reset or cable reset signals or expected goodcrc messages (goodcrc messages are only expected after the fusb305 phy has re ceived the tx message and the fusb 305 tx state?machine is in the prl_tx_wait_for_phy_response state). (note 1) (note 2)
FUSB307B www. onsemi.com 11 transmit state machine to transmit a message, the tcpm must first write the entire message in the following registers: txheadl, txheadh, txbytecnt and the txdata. the actual transmission starts when the tcpm writes the transmit register. the transmit register is where the message selection is done and it must be written once per transmission. the transmit and txbytecnt will be reset after executing a successful or failed transmission. if the transmit.retry_cnt is set to a number greater than 0, the FUSB307B will automatically retry sending the same message if a goodcrc is not received within tcrcreceivetimer. an automatic retry is not performed when sending hard?resets, cable?resets, or bist carrier mode 2 signaling. the tcpm must not write the transmit register again until alertl.i_txsucc, i_txfail, i_tx_disc have been asserted and cleared. the tcpm will not write the transmit register to request a transmission other than a hard reset until it has cleared all received message alerts. if a transmit is written when alertl.i_rxstat = 1 or alertl. i_rxhrdrst = 1, the transmit request is discarded and alertl.i_tx_disc is asserted. figure 10. receive state machine transmit[2:0] < 101b written message sent to phy crcreceivetimer timeout goodcrc response from phy layer (rxheadh[3:1] != txheadh[3:1] (messageid mismatch) | transmit[2:0] != rxstat[2:0] (sop mismatch) ) retrycounter > nretries goodcrc with messageid and sop match prl_tx_check_retrycounter actions on entry: if dfp or ufp,increment and check retrycounter prl_tx_transmission_error actions on entry: set alertl.i_txfail interrupt prl_tx_construct_message actions on entry: pass txbytecnt bytes from txheadl and txheadh and txdata to phy prl_tx_wait_for_phy_response actions on entry: initialize and run crcreceivetimer prl_tx_match_messageid actions on entry: match extracted messageid and response messageid prl_tx_message_sent actions on entry: set alertl.i_txsucc prl_tx_wait_for_ message_request actions on entry: reset retrycounter. protocoltransmit (collision detected and now bus idle) i_tx_msg_disc && bus idle retrycounter nretries protocol layer message reception in prl_rx_message_discard state 3. the crcreceivet imer is only started after the fusb305 has sent the message. if the message is not sent due to a busy channel then the crcreceivetimer will not be started. 4. this indication is sent by the phy layer when a message has been discarded due to cc being busy, and after cc becomes idle again. the crcreceivetimer is not running in this case since no message has been sent. (note 4) (note 3)
FUSB307B www. onsemi.com 12 hard reset/ cable reset state machine the tcpm will write the transmit register to initiate the hard reset/cable reset state machine, see figure 11. if a the FUSB307B is in the middle of a transmission when instructed to send a hard or cable reset, it will set the alertl.i_txdisc bit and send the hard reset signaling as soon as possible. the FUSB307B implements the hardresetcompletetimer. a hard reset or cable reset will be attempted until the hardresetcompletetimer times out. after a successful transmission or timeout, the FUSB307B will indicate that a hard reset or cable reset has been sent by asserting both alertl.i_txsucc and alertl.i_txfail registers simultaneously. the bits in rxdetect and rxbytecnt will be reset to disable pd message passing after a hard reset is received or transmitted. figure 11. hard reset and cable reset state machine transmit[2:0]=101b or 110b written hard reset or cable reset sent thardresetcomplete expires prl_hr_wait_for_hard_reset_ request prl_hr_failure actions on entry: instruct phy to stop attempting to send hard reset or cable reset. prl_hr_success actions on entry: stop thardresetcomplete timer prl_hr_construct_message actions on entry: start thardresetcomplete timer request phy to send hard reset or cable reset actions on entry: prl_hr_report actions on entry: assert alert.i_tx_succ and alert.i_tx_fail automatic goodcrc response power delivery packets require a goodcrc acknowledge packet to be sent for each received packet where the calculated crc is the correct value. this calculation is done by the FUSB307B. the FUSB307B will automatically send the goodcrc control packet in response to alleviate the local processor from responding quickly to the received packet. once the goodcrc packet is sent the FUSB307B will trigger the alertl.i_rxstat interrupt. the following sequence of events occur internally within the FUSB307B without processor intervention when it is determined that the receive message has the correct crc. if the host processor attempts a packet transmission during an automatic goodcrc response, the FUSB307B will set the alertl.i_txdisc bit interrupting the processor. the processor should only transmit a new packet once alertl.i_txsucc or alertl.i_tx_fail has been received. it is assumed that the processor will set the pwrctrl.orient to specify which channel usb?pd traffic will be transmitted or received. bist mode bist transmit the FUSB307B will transmit bist carrier mode 2 signaling when directed by the tcpm via transmit register. the FUSB307B will exit bist mode after tbistcontmode timer expires. bist receive when the FUSB307B is in bist receive mode via tcpc_ctrl register, it will acknowledge these packets with a goodcrc and automatically flush the buffer to allow for thousands of packets to be received without filling the receive buffer. bist receive mode will exit on a cable disconnect or a hard reset received. vbus source and sink control the FUSB307B can control a source and sink path via two outputs: src for the source path and snk for the sink vbus path. these two outputs are controlled via the command register. the snk and src outputs will autonomously disable upon a cable detach.
FUSB307B www. onsemi.com 13 voltage transitions the FUSB307B device can control a vsafe5v path via its src output. figure 12. transition to vsafe5v on power up power up read alert enable src path src = high FUSB307B tcpm sourcing disabled pwrstat.source_vbus = 0b pwrstat.source_hv = 0b src = low src_hv = low prepare device to source vsafe5v write: pwrctrl.dis_valarm = 1b pwrctrl.auto_disch = 0b voltage transition complete set pwrstat.source_vbus =1b set alert.i_port_pwr = 1b enable vsafe5v source write command.sourcevbusdefaultvoltage vbus > vsafe5v(min)? y no notify policy engine that voltage transition is complete transition to vsafe5v path on power up sourcing vsafe5v alert.i_port_pwr=1b? service other alerts no read alert read pwrstat yes enable auto discharge pwrctrl.auto_disch = 1b
FUSB307B www. onsemi.com 14 figure 13. transition to vsafe5v on power up accepted high voltage policy engine requests for vbus transition to high voltage read alert alert.i_valarm_hi = 1b? enable monitoring of vbus src = high monitor valarmhcfg service other alerts no FUSB307B tcpm read alert sourcing vsafe5v pwrstat.source_vbus = 1b pwrstat.source_hv = 0b (if 307/8) src = high yes enable monitoring of vbus write: pwrctrl.auto_disch = 0b pwrctrl.dis_valarm = 0b valarmhcfg = vnewsrc (min) set alertl.i_vbus_alarm_hi transition hv source enable external source path or transition existing source to hv valarmh trip? y no notify policy engine that voltage transition is complete setup fusb305 for hv sourcing write: valarml/hcfg pwrctrl.auto_disch = 1b sourcing hv via src transition to hv using src enabled path note: transitioning from hv on src to vsafe5v also on src can be done by using voltage alarm low. power supply is responsible for transitioning voltages to meet usb pd spec? no discharge necessary.
FUSB307B www. onsemi.com 15 vbus monitoring and measurement the FUSB307B can monitor the presence of vbus and will report it on pwrstat.vbus_val and interrupt alert.i_port_pwr. vbus_val is set according to vbus thresholds in vvbusthr . the FUSB307B also supports a more precise voltage measurement via an on?board adc. the voltage on vbus is measured at a rate of tvbussample and it is reported on vbus_voltage_l/h register. the precision of the measurement is +/2% with a resolution of 25 mv lsb. in addition to providing the processor an accurate measurement of vbus, the measurement in vbus_voltage will be used when monitoring various user defined thresholds: ? voltage alarms in registers valarmlcfg and valarmhcfgl ? vbus disconnect threshold in registers vbus_snk_discl and vbus_snk_disch ? vbus stop discharge threshold in registers vbus_stop_discl and vbus_stop_disch ? the FUSB307B implements low and high vbus voltage alarms that can be programmable via valarmlcfg and valarmhcfg respectively. if the high or the low thresholds are crossed, the FUSB307B will signal an interrupt on alertl.i_vbus_alrm_hi or alerth.i_vbus_alrm_lo respectively. these alarms can be disabled by writing pwrctrl.dis_valarm to one alertl.i_port_pwr is asserted if the bit?wise and of pwrstat and pwrstamsk results in any bits that have the value 1. vbus discharge manual discharge there are two types of manual discharge circuits implemented: a bleed discharge for low current and a force discharge. the bleed discharge can be manually enabled by writing a one to register bit pwrctrl.en_bleed_disch. when enabled, the bleed discharge provides a low current load on vbus of 7 k (max.) via rbleed. the force discharge is used to quickly discharge vbus to vsafe0v by applying a dynamic load to vbus via rfull_disch. the force discharge can be manually enabled by writing a one to register bit pwrctrl.force_disch. when rfull_disch is applied, the maximum slew rate allowed for discharging vbus does not exceed vsrcslewneg 30 mv/ s as it is specified in the usb?pd spec. automatic discharge bit pwrctrl. auto_disch must be disabled before enabling force discharge. automatic source discharge after a disconnect automatic discharge can be enabled by setting pwrctrl. auto_disch register bit. when in source mode the FUSB307B will fully discharge vbus to vsafe5v (max.) within tsafe5v and to vsafe0v within tsafe0v when a disconnect occurs. the FUSB307B is in source mode when the src output is asserted. the FUSB307B in source mode will detect a disconnect if the ccstat.ccx_stat field for the monitored cc pin indicates src.open and enable the full discharge pull?down device. the monitored cc pin is specified by tcpc_ctrl.orient. figure 14. vbus auto discharge as source cable disconnect (ccstat change) tsafe5v tsafe0v vsafe0v vsafe5v time vbus apply r
FUSB307B www. onsemi.com 16 automatic sink discharge after a disconnect automatic discharge can be enabled by setting pwrctrl. auto_disch register bit. when in sink mode the FUSB307B will fully discharge vbus to vsafe5v (max.) within tsafe5v and to vsafe0v within tsafe0v when a disconnect occurs. the FUSB307B is in sink mode any time msgheadr.power_role = 0. whenever the system is sinking voltages greater than vsafe5v, a disconnect will be detected based on vbus_snk_disc registers. if the system is only sinking vsafe5v, a disconnect will be detected when vbus_val goes low. due to the high capacitance on vbus (up to 100 f) the FUSB307B may not immediately know if vbus has been removed. the FUSB307B with automatic discharge on will apply rbleed discharge load to vbus until it crosses below vbus_snk_disc. the FUSB307B has to detect a disconnect within tdisconnectdetect (6 ms) from vbus crossing vbus_snk_discl. once the FUSB307B has detected a disconnect, rfull_disch will be enabled bringing the vbus voltage down to vsafe0v. whenever the FUSB307B detects a disconnect, it will not present rd (or rp) until vbus reaches vsafe0v. when the vbus voltage goes below vsafe0v, the auto?discharge circuit will disable. if the discharge of vbus to below vsafe0v is not accomplished by tsafe0v (650 ms), the FUSB307B will set the interrupt note: alertl.i_port_pwr is asserted if the bit?wise and of pwrstat and pwrstamsk results in any bits that have the value 1. alerth. i_fault bit and the status faultstat.disch_fail. the discharge circuit is not turned off when this happens. in tsinkdischar gebleed + tsinkdischar gefull have to be less than tsafe5v to comply with usb?pd spec. figure 15. vbus auto discharge as sinksource cable disconnect tsafe5v tsafe0v vsafe0v vsafe5v time vbus vbus_snk_disc tsinkdischargebleed tsinkdischarge full tdisconnectdetect apply r full_disch r bleed
FUSB307B www. onsemi.com 17 discharge during a connection the discharge functions can be manually activated via the pwrctrl.force_disch register. the discharge pull?down is specified by rfull_disch. the FUSB307B will automatically disable discharge when vbus reaches vbus_stop_disc threshold figure 16. sink discharge during a connection pwrctrl.force_disch apply r force vbus_stop_disc time vbus tsrcsettle vsrcnew sink discharge during a connection when the device is operating as a sink and it receives a hard reset or a power role swap, the automatic discharge circuitry and snk output will be disabled by the host processor to avoid a disconnect detection. watchdog timer the watchdog timer functionality is enabled whenever tcpc_ctrl.en_watchdog is set to 1b. the watchdog timer should only be enabled after an attach when the device is in attached.src, attached.snk or apply.rolecontrol states. the watchdog timer starts when any of the interrupts that are not masked in the alert register are set or when the intb pin is asserted. the watchdog timer is cleared on an i2c access by the tcpm (either read or write). if the intb pin is still asserted after this i2c access, the watchdog timer will reinitialize and start monitoring again until all of the alerts are cleared or until the intb pin is de?asserted. when the watchdog timer expires, the FUSB307B will immediately disconnect the cc terminations by setting role_control bits 3..0 to 1111b, disable all src/src_hv or snk outputs, discharge vbus to vsafe0v, and set fault_status.i2cinterfaceerror.
FUSB307B www. onsemi.com 18 usb?pd rev 3.0 features extended data messages extended data messages is only supported via chunking where large messages are broken into 2 or more 26 byte chunks. sinktx the usb?pd rev 3.0 has added this feature to allow the sink to safely transmit a message reducing the risk of collisions. the protocol layer in the source will request to set the rp value to sinktxok to indicate that the sink can initiate an atomic message sequence (ams). the protocol layer in the source will request to set the rp value to sinktxng to indicate that the sink cannot initiate an ams since the source is about to initiate an ams. the sink tcpm that desires to transmit will write the tx buffers and sink_transmit register. the FUSB307B will wait for the rp value to be set to sinktxok before transmitting the message. if rp is already set to sinktxok, a sink_transmit will transmit immediately. in the case where the sink tcpm wants to abort the message transmission before the rp value has changed to sinktxok, it can write sink_transmit.en_snk_tx = 0b. if a transmission has already started, writing this register will be ignored and a faultstat.i2c_err interrupt will be generated. if txbytecnt is less than 2h when a sink_transmit.txsop <101 is requested, a faultstat.i2cerr interrupt is generated. the alertl.i_rxstat must be cleared when sink_transmit is written or an alertl.i_tx_disc is asserted. table 4. r p settings for sink t x source rp parameter description sink operation source operation 1.5 a @5 v sinktxng sink transmit ?no go? sink cannot initiate an ams. sink can only respond to messages as part of an ams source can initiate an ams tsinktx after setting rp to this value (note 5) 3.0 a @5 v sinktxok sink transmit ?ok? sink can initiate an ams source cannot initiate an ams while this value is set 5. the tcpm is responsible for tsinktx timer. fast role swap fast role swap is the process of exchanging the source and sink roles between port partners rapidly due to the disconnection of an external power supply. the fast role swap process is intended for use by a pdusb hub that presently has an external wall supply, and is providing power both through its downstream ports to usb devices and upstream to a usb host such as a notebook. on removal of the external wall supply fast role swap enables a vbus supply to be maintained by allowing the usb host to apply vsafe5v after having detected fast role swap signaling. the initial source will signal a fast role swap request by driving cc to ground with a resistance of less than rfrswaptx for tfrswaptx . the initial source shall only signal a fast role swap when it has an explicit contract. on transmission of the fast role swap signal any pending messages will be discarded by internally toggling pd_reset. the fast role swap signal may override any active tr ansmissions. since the initial sink?s response to the fast role swap signal is to send a fr_swap message, the initial source shall ensure rp is set to sinktxok once the fast role swap signal is complete. the flow diagram in figure 17 demonstrates the hub and host function during the initial fast role swap process. the ams and power role swap necessary to complete the fast role swap is performed by the respective tcpms.
FUSB307B www. onsemi.com 19 fast role swap cable disconnect (informational only) the initial sink device waiting for frswap will not disconnect on vbus since pwrctrl.auto_disch will be set to zero by the tcpm. if the type?c cable detaches while the initial sink is ready for a frswap, it will look like the initial source has initiated a frswap; the cc lines will be driven to gnd by rd. the initial sink will perform the frswap and the tcpm will initiate the fr_swap message. since there is no device attached, there will be no goodcrc response which will transition to t ype?c error recovery. figure 17. fast role swap flow diagram sourcing vbus swap request detected issue a pd_reset snk = low (fusb305/6) src = high interrupt alert_vd.swap_rx hub fusb305/6/7 initially acting as source sinking vbus system loses power source initiate fast swap signal hub tcpm writes: src_frswap.frswap = 1b fusb30x will: drive src = 0b issue a pd_reset drive cc to gnd with rfrswaptx cc < vfrswapcabletx debounced for tfrswaprx ? y no host fusb305/6/7 initially acting as sink prepare system for frswap host tcpm writes: snk_frswap.en_swap_dtct pwrctrl.auto_disch=0b source parameters rfrswaptx ?> 5 ohm (max) sink parameters tfrswaprx -> 30us (min) to 50 s(max) vfrswapcabletx ?> 490mv (min), 520mv (typ), 550mv (max) frswap drives cc line that is transmitting bmc low with rfrswaptx for tfrswaptx sinking vbus discard any pending pd messages tfrswaptx done? y no if (!src_frswap.manual_snk_en) wait frswap_snk_delay[1:0] start sinking if(src_frswap.manual_snk_en) hub tcpm writes: command.sinkvbus else {drive snk=1b set pwrstat.snkvbus=1} set rp to sinktxok hub tcpm writes: rolectrl.rp_val = 10b drive snk = 1b set pwrstat.snkvbus = 1 (!src_frswap.manual_snk_en && frwap_snk_delay == 00b)? y no tfrswaptx ?> 60 s (min) to 120 s (max) tsrcfrswap ?> 150 s (max) ? ? ?
FUSB307B www. onsemi.com 20 table 5. absolute maximum ratings symbol parameter min max unit v ddamr supply voltage from vdd ?0.5 6.0 v v cc_hddrp (note 6) cc pins when configured as host, device or dual role port ?0.5 6.0 v v vbus vbus supply voltage ?0.5 28.0 v t storage storage temperature range ?65 +150 c t j maximum junction temperature +150 c t l lead temperature (soldering, 10 seconds) +260 c esd human body model, jedec jesd22?a114 connector pins (vbus, ccx) 4 kv others 2 kv charged device model, jedec lesd22?c101 all pins 1 kv stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device function ality should not be assumed, damage may occur and reliability may be affected. 6. as host, device drives cc, vconn. table 6. recommended operating conditions symbol parameter min typ max unit v bus vbus supply voltage (note 7) 4.0 5.0 21.5 v v dd vdd supply voltage 2.8 (note 8) 3.3 5.5 v v conn vconn supply voltage (note 9) 2.7 5.5 v i conn vconn supply current 560 ma t a operating temperature ?40 +85 c t a operating temperature (note 10) ?40 +105 c functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. 7. 20 v pd + 5% tolerance per spec + 0.5 v load transition. 8. this is for functional operation only and isn?t the lowest limit for all subsequent electrical specifications below. all electrical par ameters have a minimum of 3 v operation. 9. for powered accessories vconn minimum is 2.7 v. 10. automotive part only, FUSB307Bvmpx.
FUSB307B www. onsemi.com 21 dc and transient characteristics unless otherwise specified: recommended t a and t j temperature ranges. all typical values are at t a = 25 c and v dd = 3.3 v unless otherwise specified. table 7. current consumption symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max i disable disable current (rolectrl = 0x0f) 10 a i stby unattached sink 6 10 a unattached drp or source 7 20 a i attach_ typec attached as sink (no pd, auto_disch = 0) 11 26 a attached as source (no pd) 12 22 a table 8. baseband pd symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max ui unit interval 3.03 3.33 3.70 s transmitter zdriver tx output impedance at 750 khz with an external 220 pf or equivalent load 33 75 tenddrivebmc time to cease driving the line after the end of the last bit of the frame 2 ui tholdlowbmc time to cease driving the line after the final high?to?low transition 1 s tstartdrive time before the start of the first bit of the preamble when the transmitter shall start driving the line ?1 1 s tbistcontmode time a bist carrier mode 2 transmission is performed 30 60 ms tbuffer2cc time from i2c stop from writing to transmit register to first bit of preamble transmitted 195 s t r rise time 300 ns t f fall time 300 ns receiver creceiver receiver capacitance when driver isn?t turned on (note 11) 25 pf zbmcrx receiver input impedance 1 m tcc2buffer time between last bit of eop to i_rxstat 50 s trxfilter rx bandwidth limiting filter (note 11) 100 ns ntransitioncount transitions count in a time window of 20 s max 3 edges ttransitionwindow time window for detecting non?idle 12 20 s 11. guaranteed by characterization and/or design. not production tested .
FUSB307B www. onsemi.com 22 figure 18. transmitter test load vcom creceiver vcom creceiver ccableplug ccableplug switch drp drp switch cable connector connector table 9. usb-pd r3.0 specific parameters symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max transmitter rfrswaptx fast role swap request transmit driver resistance measured from v ccx = 0 to vfrswapcabletx 5 tfrswaptx fast role swap request transmit duration 60 120 s receiver tfrswaprx fast role swap request detection time 30 50 s vfrswapcabletx fast role swap request voltage detection threshold 490 520 550 mv table 10. type c specific parameters symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max r sw_ccx r dson for vconn to cc1 or vconn to cc2 0.4 1.0 i sw_ccx over current protection (ocp) limit at which vconn switch shuts off over the entire vconn voltage range vconn_ocp = 0fh 600 800 1000 ma t softstart time taken for the vconn switch to turn on during which over? current protection is disabled 1.5 ms i 80_ccx dfp 80 a cc current (default) rolectrl = 05h 64 80 96 a i 180_ccx dfp 180 a cc current (1.5 a) rolectrl = 15h 166 180 194 a i 330_ccx dfp 330 a cc current (3 a) rolectrl = 25h 304 330 356 a v ufpdb ufp pull?down voltage in dead battery under all pull?up dfp loads 2.18 v r device device pull?down resistance (note 12) 4.6 5.1 5.6 k ra powered accessory termination 800 1200 vra?srcdef ra detection threshold for cc pin for source for default current on vbus 0.15 0.20 0.25 v vra?src1.5a ra detection threshold for cc pin for source for 1.5 a current on vbus 0.35 0.40 0.45 v
FUSB307B www. onsemi.com 23 table 10. type c specific parameters (continued) symbol unit t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c parameter symbol unit max typ min parameter vra?src3a ra detection threshold for cc pin for source for 3 a current on vbus 0.75 0.80 0.85 v vrd?srcdef rd detection threshold for source for default current (host_cur1/0 = 01) 1.50 1.60 1.65 v vrd?src1.5a rd detection threshold for source for 1.5 a current (host_cur1/0 = 10) 1.50 1.60 1.65 v vrd?src3a rd detection threshold for source for 3 a current (host_cur1/0 = 11) 2.45 2.60 2.75 v vra?snk ra detection threshold for cc pin for sink 0.15 0.20 0.25 v vrd?def rd default current detection threshold for sink 0.61 0.66 0.70 v vrd?1.5a rd 1.5 a current detection threshold for sink 1.16 1.23 1.31 v vrd?3.0a rd 3 a current detection threshold for sink 2.04 2.11 2.18 v zopen cc resistance for disabled state, rolectrl = 0fh 126 k vvconnthr valid vconn voltage assumes pwrctrl.en_vconn = 1b 2.4 v ttcpcfilter debounce time on cc lines to prevent ccstat change in case of minor changes in voltage on cc because of noise 4 500 s tccdebounce debounce time for cc attach detection 100 150 200 ms tpddebounce (note 13) time a port shall wait before it can determine there has been a change in usb type?c current due to the potential for usb?pd bmc signaling on cc 10 15 20 ms tsetreg time between cc status change and i2c registers updated 50 s ttcpcsamplerate cc sample rate for indicating changes on cc lines 1 ms tdrp sum of ttogglesrc and ttogglesnk timers 50 100 ms ttogglesrc time spent in apply rp before transitioning to apply rd drptoggle = 00 15 30 ms drptoggle = 01 20 40 ms drptoggle = 10 25 50 ms drptoggle = 11 30 60 ms ttogglesnk time spent in apply rd before transitioning to apply rp drptoggle = 00 35 70 ms drptoggle = 01 30 60 ms drptoggle = 10 25 50 ms drptoggle = 11 20 40 ms 12. rdevice minimum and maximum specifications are only guaranteed when power is applied. 13. only applicable to autonomous debug state machine.
FUSB307B www. onsemi.com 24 table 11. vbus measurement characteristics symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max vmdacstepvbus vbus measure block lsb reported on vbus_voltage[9:0] register 25 mv pmdacvbus accuracy of vbus voltage measuremen t t a = ?40 to +85 c 2 % t a = +85 to +105 c (note 12) 5 % tvbussample sampling period of vbus measurement 3 ms vvbusthr vbus threshold at which vbus_val interrupt is triggered. assumes vbus present detection is enabled vdd > v ddgood 3.5 4.0 (note 14) v vdd < v ddgood (dead battery) 3.4 4.0 vvbushys hysteresis on vbus comparator 50 mv vsafe0vthr safe operating voltage at ?zero volts? threshold 0.8 v vsafe0vhys vsafe0v hysteresis 40 mv valarmlsb lsb of vbus thresholds for vbus_snk_discl vbus_stop_discl valarmhcfgl valarmlcfgl 50 mv palarm accuracy of vbus thresholds for vbus_snk_discl vbus_stop_discl valarmhcfgl valarmlcfgl 5 % 14. FUSB307Bvmpx vvbusthr (max) = 4.05 v.
FUSB307B www. onsemi.com 25 table 12. source and sink control specifications symbol parameter t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c min typ max unit r bleed equivalent resistance for bleed discharging vbus vbus = 4.0 v to 21.5 v 4 7 k vsrcslewneg maximum slew rate allowed when discharging vbus vbus = 4.0 v to 21.5 v 30 mv/ s tsafe0v time to reach vsafe0v max 650 ms tsafe5v time to reach vsafe5v max 275 ms tsrcsettle time to discharge to vsrcnew 275 ms tauto_disch_fail time to declare auto discharge failure to discharge to vsafe0v device configured as source. measure from ccstat change to open 650 ms device configured as sink. measure from i_vbus_snk_disc 440 ms tauto_disch_fail_5v time to declare auto discharge failure to discharge to vsafe5v device configured as source. measure from ccstat change to open 275 ms device configured as sink. measure from i_vbus_snk_disc 60 ms table 13. ldo specifications symbol parameter v dd conditions t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max unit v v3p3 ldo output voltage < v ddgood vbus = 4.0 v to 21.5 v 3.0 3.6 v v ldo_valid valid vbus_in range for ldo operation < v ddgood 4.0 21.5 v v ddgood vdd voltage where device is powered from vdd instead of vbus 2.7 3.0 v i ldo_max max. output current < v ddgood vbus = 4.0 v to 21.5 v, v drop = 120 mv 30 ma table 14. over-temperature specifications symbol parameter min typ max unit t shut temp. for vconn switch turn off 145 c t hys temp. hysteresis for vconn switch turn on 10 c table 15. watchdog timer specifications symbol parameter min typ max unit t hvwatchdog time from last i2c transaction or intb pin as- sertion to entering errorrecovery 1500 2000 ms
FUSB307B www. onsemi.com 26 table 16. io specifications symbol parameter v dd (v) conditions t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min typ max host interface pins(int_n, dbg_n) v olintn output low voltage 3.0 to 5.5 i ol = 4 ma 0.4 v gpios, orient and mux_sel pins v il low?level input voltage 3.0 to 5.5 0.4 v v ih high?level input voltage 3.0 to 5.5 1.2 v v ol low?level output voltage 3.0 to 5.5 i ol = 4 ma 0.4 v v oh high?level output voltage 3.0 to 5.5 i oh = ?2 ma 0.7v dd v i in input leakage 3.0 to 5.5 input voltage 0 v to 5.5 v (when gpio is setup as an input or tri?stated output) ?5 5 a i off off input leakage 0 input voltage 0 v to 5.5 v ?5 5 a src, snk and src_hv v ol low?level output voltage 3.0 to 5.5 i ol = 4 ma 0.4 v v oh high?level output voltage 3.0 to 5.5 i oh = ?2 ma 0.7v dd v i 2 c interface pins ? standard, fast or fast mode plus speed mode sda, scl) (note 15) v ddext external power supply to which sda and scl are pulled up 1.8 3.6 v symbol parameter v dd (v) conditions t a = ?40 to +85 c t a = ?40 to +105 c (note 17) t j = ?40 to +125 c unit min. typ. max. v ili2c low?level input voltage 3.0 to 5.5 0.4 v v ihi2c high?level input voltage 3.0 to 5.5 1.2 v v hys hysteresis of schmitt trigger inputs 3.0 to 5.5 0.2 v i i2c input current of sda and scl pins, 3.0 to 5.5 input voltage 0.26 v to 2 v ?10 10 a i ccti2c vdd current when sda or scl is high 3.0 to 5.5 input voltage 1.8 v ?10 10 a v olsda low?level output voltage at 2 ma sink current (open?drain) 3.0 to 5.5 0 0.36 v i olsda low?level output current (open?drain) 3.0 to 5.5 v olsda = 0.4 v 20 ma c i capacitance for each i/o pin (note 16) 3.0 to 5.5 5 pf 15. i 2 c pull up voltage is required to be between 1.71 v and v dd .
FUSB307B www. onsemi.com 27 table 17. fast mode plus i 2 c specifications symbol parameter fast mode plus min. max. unit f scl i2c_scl clock frequency 0 1000 khz t hd;sta hold time (repeated) start condition 0.26 s t low low period of i2c_scl clock 0.5 s t high high period of i2c_scl clock 0.26 s t su;sta set?up time for repeated start condition 0.26 s t hd;dat data hold time 0 s t su;dat data set?up time 50 ns t r rise time of i2c_sda and i2c_scl signals 20 (v dd /5.5 v) 120 ns t f fall time of i2c_sda and i2c_scl signals (note 16) 20 (v dd /5.5 v) 120 ns t su;sto set?up time for stop condition 0.26 s t buf bus?free time between stop and start conditions 0.5 s t sp pulse width of spikes that must be suppressed by the input filter 0 50 ns 16. g uaranteed by characterization. not production tested. 17. automotive part only, FUSB307Bvmpx. figure 19. definition of timing for full?speed mode devices on the i2c bus sda scl sda scl 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% 70% 30% p s 002aac938 1 / f scl s sr t f t r t su;dat t vd;dat t hd;dat t f t hd;sta t low t r t high t hd;sta t su;sta t sp t vd;ack t hd;sto t buf 1 st clock cycle 9 th clock 9 th clock v il = 0.3v dd v ih = 0.7v dd
www. onsemi.com 28 table 18. register definitions address register name type rst val bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 00h vendidl r 79h vendor id low 01h vendidh r 07h vendor id high 02h prodidl r 33h product id low 03h prodidh r 01h product id high 04h devidl r 02h device id low 05h devidh r 02h device id high 06h typecrevl r 12h usb type?c revision low 07h typecrevh r 00h usb type?c revision high 08h usbpdver r 12h usb pd version 09h usbpdrev r 20h usb pd revision 0ah pdifrevl r 12h usb pd interface revision low (version) 0bh pdifrevh r 10h usb pd interface revision high (revision) 10h alertl r/wc 00h i_vbus_ alrm_hi i_txsucc i_txdisc i_txfail i_ rxhrdrst i_rxstat i_port_ pwr i_ccstat 11h alerth r/wc 00h i_vd_ alert reserved reserved reserved i_vbus_ snk_disc i_rx_full i_fault i_vbus_ alrm_lo 12h alertmskl r/w ffh m_vbus_ alrm_hi m_txsucc m_tx_disc m_txfail m_ rxhrdrst m_rxstat m_port_ pwr m_ccstat 13h alertmskh r/w 0fh m_vd_ alert reserved reserved reserved m_vbus_ snk_disc m_rx_full m_fault m_vbus_ alrm_lo 14h pwrstatmsk r/w ffh m_debug_ acc m_init m_src_hv m_src_ vbus m_vbus_ val_en m_vbus_ val m_vconn_ val m_ snkvbus 15h faultstatmsk r/w b3h m_all_ regs_ reset reserved m_auto_ disch_fail m_force_ disch_fail reserved reserved m_vconn_ ocp m_i2c_err 16h..17h reserved r 00h reserved 18h std_out_cfg r/w 40h tri_state debug_ acc reserved reserved mux_ctrl reserved orient 19h tcpc_ctrl r/w 00h reserved en_ watchdog debug_ acc_ctrl i2c_clk_strecth bist_ tmode orient 1ah rolectrl r/w 0ah 4ah reserved drp rp_val cc2_term cc1_term
www. onsemi.com 29 table 18. register definitions (continued) address bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 rst val type register name 1bh faultctrl r/w 00h reserved reserved disch_ timer_dis reserved reserved vconn_ ocp_dis 1ch pwrctrl r/w 60h reserved vbus_mon dis_valrm auto_ disch en_bleed_ disch force_ disch vconn_ pwr en_vconn 1dh ccstat r 00h/20h reserved look4con con_res cc2_stat cc1_stat 1eh pwrstat r 08h debug_ acc tcpc_init source_ hv source_ vbus vbus_val_ en vbus_val vconn_ val snkvbus 1fh faultstat r 80h all_regs_ reset reserved auto_ disch_fail force_ disch_fail reserved reserved vconn_ ocp i2c_err 20h..22h reserved r 00h reserved 23h command r 00h command 24h devcap1l r ddh roles_support roles_ support switch_ vconn snk_vbus src_hv src_vbus 25h devcap1h r 1eh reserved bleed_dis force_dis vbus_ meas_ alrm rp_support 26h devcap2l r d7h snk_disc_ detect stop_ disch vbus_alrm_lsb vconn_power_cap vconn_ fault_cap 27h devcap2h r 01h reserved watchdog timer 28h std_in_cap r 00h reserved 29h std_out_cap r 41h reserved debug_ acc reserved mux_ctrl reserved orient 2ah..2dh reserved r 00h reserved 2eh msgheadr r/w 02h reserved cable plug data role usb pd rev pwr role 2fh rxdetect r/w 00h reserved en_cable_ rst en_hrd_ rst en_sop2_ dbg en_sop1_ dbg en_sop2 en_sop1 en_sop 30h rxbytecnt r 00h received byte count 31h rxstat r 00h reserved received sop* message 32h rxheadl r 00h received header low 33h rxheadh r 00h received header high 34h..4fh rxdata r 00h received data payload 50h transmit r/w 00h reserved retry counter reserved transmit sop* message
www. onsemi.com 30 table 18. register definitions (continued) address bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 rst val type register name 51h txbytecnt r/w 00h transmit byte count 52h txheadl r/w 00h transmit header low 53h txheadh r/w 00h transmit header high 54h..6f txdata r/w 00h transmit payload 70h vbus_voltage_l r 00h vbus measurement output 71h vbus_voltage_h r 00h 72h vbus_snk_discl r/w a0h vbus sink disconnected threshold (see register description table) 73h vbus_snk_disch r/w 1ch 74h vbus_stop_discl r/w 00h vbus discharge stop threshold (see register description table) 75h vbus_stop_disch r/w 00h 76h valarmhcfgl r/w 00h voltage high trip point (see register description table) 77h valarmhcfgh r/w 00h 78h valarmlcfgl r/w 00h voltage low trip point (see register description table) 79h valarmlcfgh r/w 00h 7ah..7fh reserved r/w 00h reserved a0h vconn_ocp r/w 0fh reserved ocp_ range ocp_cur a2h reset r/wc 00h reserved pd_rst sw_rst a4h gpio1_cfg r/w 00h reserved gpo1_val gpi1_en gpo1_en a5h gpio2_cfg r/w 00h reserved fr_swap_ fn gpo2_val gpi2_en gpo2_en a6h gpio_stat r 00h reserved gpi2_val gpi1_val a7h drptoggle r/w 00h reserved drptoggle a9h..afh reserved r 00h reserved b0h sink_transmit r/w 40h reserved dis_snk_ tx retry counter reserved transmit sop* message b1h src_frswap r/w 00h reserved frswap_snk_delay manual_ snk_en fr_swap b2h snk_frswap r/w 00h reserved en_ frswap_ dtct
www. onsemi.com 31 table 18. register definitions (continued) address bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 rst val type register name b3h alert_vd r/w 00h reserved i_disch_ succ i_gpi2 i_gpi1 i_vdd_ dtct i_otp i_swap_tx i_swap_rx b4h alert_vd_msk r/w 7fh reserved m_disch_ succ m_gpi2 m_gpi1 mi_vdd_ dtct m_otp m_swap_ tx m_swap_ rx
www. onsemi.com 32 table 19. vendidl address: 00h reset value: 0x79 type: read bit # name r/w/c size (bits) vendor id low description 7:0 vendidl r 8 on semiconductor vendor id low: 79h table 20. vendidh address: 01h reset value: 0x07 type: read bit # name r/w/c size (bits) vendor id high description 7:0 vendidh r 8 on semiconductor vendor id high: 07h table 21. prodidl address: 02h reset value: see below type: read bit # name r/w/c size (bits) product id low description 7:0 prodidl r 8 product id low, FUSB307B: 33h table 22. prodidh address: 03h reset value: 0x01h type: read bit # name r/w/c size (bits) product id high description 7:0 prodidh r 8 product id high, all: 1h table 23. devidl address: 04h reset value: 0x02h type: read bit # name r/w/c size (bits) device id low (version) description 7:0 devidl r 8 version id: 02h a_[revision id]: 0x01 (e.g. a_reva) b_[revision id]: 0x02 (e.g. b_reva) c_[revision id]: 0x03 (e.g. c_reva) etc table 24. devidh address: 05h reset value: 0x02h type: read bit # name r/w/c size (bits) device id high (revision) description 7:0 devidh r 8 revision id: 02h [version id]_reva: 0x00 (e.g. a_reva) [version id]_revb: 0x01 (e.g. a_revb) [version id]_revc: 0x02 (e.g. a_revc) etc
www. onsemi.com 33 table 25. typecrevl address: 06h reset value: 0x12h type: read bit # name r/w/c size (bits) type?c revision low description 7:0 typecrevl r 8 type?c revision low: 12h table 26. typecrevh address: 07h reset value: 0x00h type: read bit # name r/w/c size (bits) type?c revision high description 7:0 typecrevh r 8 type?c revision high: 00h table 27. usbpdver address: 08h reset value: 0x12h type: read bit # name r/w/c size (bits) usb?pd version description 7:0 usbpdver r 8 usb?pd version: 12h table 28. usbpdrev address: 09h reset value: 0x20h type: read bit # name r/w/c size (bits) usb?pd revision description 7:0 usbpdrev r 8 usb?pd revision: 20h table 29. pdifrevl address: 0ah reset value: 0x12h type: read bit # name r/w/c size (bits) usb?pd interface revision low description 7:0 pdifrevl r 8 usb?pd if version: 12h table 30. pdifrevh address: 0bh reset value: 0x10h type: read bit # name r/w/c size (bits) usb?pd interface revision high description 7:0 pdifrevh r 8 usb?pd if revision: 10h
www. onsemi.com 34 table 31. alertl address: 10h reset value: 0x00 type: read, write 1 to clear bit # name r/w/c size (bits) alert1 description 7 i_vbus_alrm_hi r/wc 1 voltage alarm hi 0b: cleared 1b: a high?voltage alarm has occurred 6 i_txsucc r/wc 1 0b: cleared 1b: reset or sop* message transmission successful. goodcrc response received on sop* message transmission. transmit sop* message buffer registers are empty 5 i_txdisc r/wc 1 0b: cleared 1b: reset or sop* message transmission not sent due to incoming receive message. transmit sop* message buffer registers are empty 4 i_txfail r/wc 1 0b: cleared 1b: sop* message transmission not successful, no goodcrc re- sponse received on sop* message transmission. transmit sop* message buffer registers are empty. 3 i_rxhrdrst r/wc 1 received hard reset 0b: cleared 1b: received hard reset message 2 i_rxstat r/wc 1 receive status 0b: cleared 1b: rxstat changed. rxbytecnt being 0 does not set this regis- ter 1 i_port_pwr (note 18) r/wc 1 port power status 0b: cleared 1b: port status changed. read pwrstat register 0 i_ccstat r/wc 1 cc status 0b: cleared 1b: cc status changed. read ccstat register 18. alertl.i_port_pwr is asserted if the bit?wise and of pwrstat and pwrstamsk results in any bits that have the value 1 . i_vbus_snk_disc
www. onsemi.com 35 table 32. alerth address: 11h reset value: 0x00 type: read, write 1 to clear bit # name r/w/c size (bits) alert2 description 7 i_vd_alert rwc 1 vendor defined alert 0b: cleared 1b: a vendor defined alert has occurred. read alert_vd register 6:4 reserved r 3 reserved: 000b 3 i_vbus_snk_disc rwc 1 vbus sink disconnect detected 0b: cleared 1b: a vbus sink disconnect threshold crossing from high to low has been detected 2 i_rx_full rwc 1 rx buffer overflow 0b: internal rx buffer is functioning properly 1b: internal rx buffer has overflowed note: this interrupt indicates overflow of the internal buffer, not the rxdata space. to clear overflow condition, write to alertl.i_rx- stat writing a 1 to this register acknowledges the overflow. the actual overflow is cleared by writing to alertl. i_rxstat 1 i_fault (note 19) r/wc 1 fault alarm 0b: cleared 1b: a fault alarm has occurred. read faultstat register 0 i_vbus_alrm_lo r/wc 1 voltage alarm lo 0b: cleared 1b: a low?voltage alarm has occurred 19. alerth.i_fault is asserted if the bit?wise and of faultstat and faultstamsk results in any bits that have the value 1. table 33. alertmskl address: 12h reset value: 0xff (resets on por, sw_rst and hard reset) type: read/write bit # name r/w/c size (bits) alert mask 1 description 7 m_vbus_alrm_hi r/w 1 0b: interrupt masked 1b: interrupt unmasked 6 m_txsucc r/w 1 0b: interrupt masked 1b: interrupt unmasked 5 m_tx_disc r/w 1 0b: interrupt masked 1b: interrupt unmasked 4 m_txfail r/w 1 0b: interrupt masked 1b: interrupt unmasked 3 m_rxhrdrst r/w 1 0b: interrupt masked 1b: interrupt unmasked note: generally this interrupt should not be masked 2 m_rxstat r/w 1 0b: interrupt masked 1b: interrupt unmasked 1 m_port_pwr r/w 1 0b: interrupt masked 1b: interrupt unmasked 0 m_ccstat r/w 1 0b: interrupt masked 1b: interrupt unmasked
www. onsemi.com 36 table 34. alertmskh address: 12h reset value: 0xff (resets on por, sw_rst and hard reset) type: read/write bit # name r/w/c size (bits) alert mask 2 description 7 m_vd_alert rw 1 0b: interrupt masked, 1b: interrupt unmasked 6:4 reserved r 3 reserved: 000b 3 m_vbus_snk_disc rw 1 0b: interrupt masked, 1b: interrupt unmasked 2 m_rx_full rw 1 0b: interrupt masked, 1b: interrupt unmasked 1 m_fault rw 1 0b: interrupt masked, 1b: interrupt unmasked 0 m_vbus_alrm_lo rw 1 0b: interrupt masked, 1b: interrupt unmasked table 35. pwrstatmsk address: 14h reset value: 0xff (resets on por, sw_rst and hard reset) type: read/write bit # name r/w/c size (bits) power status mask description 7 m_debug_acc rw 1 debug accessory connected interrupt mask 0b: interrupt masked 1b: interrupt unmasked 6 m_init rw 1 tcpc initialization interrupt mask 0b: interrupt masked 1b: interrupt unmasked 5 m_src_hv rw 1 sourcing high voltage interrupt mask 0b: interrupt masked 1b: interrupt unmasked 4 m_src_vbus rw 1 sourcing vbus interrupt mask 0b: interrupt masked 1b: interrupt unmasked 3 m_vbus_val_en rw 1 vbus valid detection status interrupt mask 0b: interrupt masked 1b: interrupt unmasked 2 m_vbus_val rw 1 vbus valid status interrupt mask 0b: interrupt masked 1b: interrupt unmasked 1 m_vconn_val rw 1 v conn present status interrupt mask 0b: interrupt masked 1b: interrupt unmasked 0 m_snkvbus rw 1 sinking vbus status interrupt mask 0b: interrupt masked 1b: interrupt unmasked
www. onsemi.com 37 table 36. faultstatmsk address: 15h reset value: 0xb3 (resets on por, sw_rst and hard reset) type: read/write bit # name r/w/c size (bits) fault status mask description 7 m_all_regs_reset rw 1 all registers reset to default 0b: interrupt masked 1b: interrupt unmasked 6 reserved r 1 reserved: 0b 5 m_auto_disch_fail rw 1 auto discharge fail interrupt mask 0b: interrupt masked 1b: interrupt unmasked 4 m_force_disch_fail rw 1 force discharge fail interrupt mask 0b: interrupt masked 1b: interrupt unmasked 3 reserved r 1 reserved: 0b 2 reserved r 1 reserved: 0b 1 m_vconn_ocp rw 1 vconn ocp interrupt mask 0b: interrupt masked 1b: interrupt unmasked 0 m_i2c_error rw 1 i2c interface error interrupt mask 0b: interrupt masked 1b: interrupt unmasked table 37. std_out_cfg address: 18h reset value: 0x40 type: read/write bit # name r/w/c size (bits) standard outputs configuration 7 tri_state r/w 1 0b: standard output control 1b: force all outputs to tri?state 6 debug_acc r/w 1 0b: debug connected output is driven low 1b: no debug accessory connected output is driven high note: the FUSB307B ignores writes to this bit if tcpc_ctrl.debug_acc_ctrl = 0b 5 reserved r 1 reserved: 0b 4 reserved r 1 reserved: 0b 3:2 mux_ctrl r/w 2 controls mux_s0 and mux_s1 outputs. 00b: mux_s0 = 0, mux_s1 = 0. no connection. 01b: mux_s0 = 1, mux_s1 = 0. usb3.1 connected 10b: mux_s0 = 0, mux_s1 = 1. dp alternate mode ? 4 lanes 11b: mux_s0 = 1, mux_s1 = 1. usb3 .1 + display port lanes 0 & 1 1 reserved r 1 reserved: 0b 0 orient r/w 1 controls orient output 0b: normal (cc1 = a5, cc2 = b5, tx1 = a2/a3, rx1 = b10/b11) 1b: flipped (cc2 = a5, cc1 = b5, tx1 = b2/b3, rx1 = a10/a11)
www. onsemi.com 38 table 38. tcpc_ctrl address: 19h reset value: 0x00 (por, and sw_rst) type: read/write bit # name r/w/c size (bits) tcpc control register 7:4 reserved r 2 reserved: 00b 5 en_watchdog r/w 1 0b: watchdog monitoring is disabled (default) 1b: watchdog monitoring is enabled 4 debug_acc_ctrl r/w 1 debug accessory control 0b: standard output is controlled by FUSB307B 1b: standard output is controlled by external processor note: see: debug accessory state machine 3:2 i2c_clk_stretch r 2 00b: i2c clock stretching is disabled. writing to these register bits will be ignored. 1 bist_tmode r/w 1 bist test data receive enable 0b: normal operation. incoming messages are stored and passed to host 1b: bist test mode. receive buffer is cleared immediately after goodcrc response. 0 orient r/w 1 plug orientation 0b: when vconn is enabled, apply it to the cc2 pin. monitor the cc1 pin for bmc communications if pd messaging is enabled. 1b: when vconn is enabled, apply it to the cc1 pin. monitor the cc2 pin for bmc communications if pd messaging is enabled. table 39. rolectrl address: 1ah reset value (note 19) 0x0a for FUSB307B device in dead battery, 0x4a for non?dead?battery. type: read/write bit # name r/w/c size (bits) role control description 7 reserved r 1 reserved: 0b 6 drp (notes 21, 22) r/w 1 0b: no drp. bits b3..0 determine rp/rd/ra settings 1b: drp 5:4 rp_val r/w 2 00b: rp default 01b: rp 1.5 a 10b: rp 3.0 a 11b: reserved 3:2 cc2_term (notes 23, 24) r/w 2 00b: ra 01b: rp (use rp definition in b5..4) 10b: rd 11b: open (disconnect or don?t care) 1:0 cc1_term (notes 23, 24) r/w 2 00b: ra 01b: rp (use rp definition in b5..4) 10b: rd 11b: open (disconnect or don?t care) 20. reset values are loaded on either vbus or vdd power up. dead battery reset values loaded on vbus power up will be maintained when battery is eventually present. 21. rp value is defined in b5..4 when performing the drp toggling as well as when a connection is resolved. 22. the FUSB307B toggles cc1 & cc2 after receiving a.look4con and until a connection is detected. upon connection, the FUSB307B resolves to either an rp or rd and report the cc1/cc2 state in the ccstat register. the FUSB307B will continue to present the r esolved rd or rp regardless of any changes voltage on the cc wires. 23. when ccx_term bits are set to open and drp = 0, the phy and cc comparators will power down. 24. if drp = 1, look4con starts toggling with the value set in cc1_term/cc2_term. if cc1_term/cc2_term is different than rp/rp or rd/rd, the command will be ignored.
www. onsemi.com 39 table 40. faultctrl address: 1bh reset value: 0x00 type: read/write bit # name r/w/c size (bits) fault control description 7:4 reserved r 4 reserved: 0000b 3 disch_timer_dis r/w 1 auto and force vbus discharge timer enable 0b: vbus discharge timer is enabled 1b: vbus discharge timer is disabled 2 reserved r 1 reserved: 0b 1 reserved r 1 reserved: 0b 0 vconn_ocp_dis r/w 1 vconn ocp enable 0b: vconn ocp enabled 1b: vconn ocp disabled table 41. pwrctrl address: 1ch reset value: 0x60 type: read/write bit # name r/w/c size (bits) power control description 7 reserved r 1 reserved: 0b 6 dis_vbus_mon (note 25) r/w 1 controls vbus_voltage_l monitoring. 0b: vbus voltage monitoring is enabled 1b: vbus voltage monitoring is disabled 5 dis_valarm r/w 1 disables valarmhcfgl and valarmlcfgl 0b: voltage alarm reporting is enabled 1b:voltage alarm reporting is disabled 4 auto_disch (notes 26, 28) r/w 1 auto discharge on disconnect 0b: turn off automatically discharge vbus based on vbus voltage 1b: turn on automatically discharge vbus based on vbus voltage 3 en_bleed_disch (note 30) r/w 1 enable bleed discharge 0b: disable bleed discharge of vbus 1b: enable bleed discharge of v bus 2 force_disch (note 27, 29) r/w 1 force discharge 0b: disable forced discharge of vbus 1b: enable forced discharge of v bus 1 vconn_pwr r/w 1 v conn power supported writing this bit has no function. please use vconn_ocp to set ocp values 0 en_vconn r/w 1 enable v conn 0b: disable v conn source (default) 1b: enable v conn source to cc 25. if vbus_mon is disabled, vbus_voltage_l and vbus_voltage_h reports all zeroes. 26. setting this bit in a source FUSB307B triggers the following actions upon disconnection detection: 1. disable sourcing power over vbus 2. vbus discharge 27. sourcing power over vbus shall be disabled before or at same time as starting vbus discharge. 28. setting this bit in a sink FUSB307B triggers the following action upon disconnection detection: 1. vbus discharge 29. the FUSB307B will automatically disable discharge once the voltage on vbus is below vsafe0v (max.). 30. bleed discharge is a low current discharge to provide a minimum load current if needed.
www. onsemi.com 40 table 42. ccstat address: 1dh reset value: 0x00 type: read bit # name r/w/c size (bits) cc status description (note 31) 7:6 reserved r 2 reserved: 00b 5 look4con r 1 0b: the FUSB307B is not looking for connection or indicated a potential connection has been found when transitioned from a 1 to 0 1b: the FUSB307B looking for connection 4 con_res r 1 0b: the FUSB307B is presenting rp 1b: the FUSB307B is presenting rd this bit is only valid if the FUSB307B was a drp and has stopped drp toggling 3:2 cc2_stat r 2 if (role_control.cc2 = rp) or (con_res = 0) 00b: src.open (open, rp) 01b: src.ra (below maximum vra) 10b: src.rd (within the vrd range) 11b: reserved if (role_control.cc2 = rd) or (con_res = 1) 00b: snk.open (below maximum vra) 01b: snk.default (above minimum vrd?connect) 10b: snk.power1.5 (above minimum vrd?connect) detects rp 1.5 a 11b: snk.power3.0 (above minimum vrd?connect) detects rp 3.0 a if role_control.cc2=ra, this field is set to 00b if role_control.cc2=open, this field is set to 00b this field always returns 00b if (look4con = 1) or (pwrctrl.en_vconn = 1 and tcpc_control.plugorientation = 0). otherwise, the returned value depends upon role_control.cc2. 1:0 cc1_stat r 2 if (role_control.cc1 = rp) or (con_res = 0) 00b: src.open (open, rp) 01b: src.ra (below maximum vra) 10b: src.rd (within the vrd range) 11b: reserved if (role_control.cc1 = rd) or con_res = 1) 00b: snk.open (below maximum vra) 01b: snk.default (above minimum vrd?connect) 10b: snk.power1.5 (above minimum vrd?connect) detects rp?1.5 a 11b: snk.power3.0 (above minimum vrd?connect) detects rp?3.0 a if role_control.cc1 = ra, this field is set to 00b if role_control.cc1 = open, this field is set to 00b this field always returns 00b if (look4con = 1) or (pwrctrl.en_vconn = 1 and tcpc_control.plugorientation = 0). otherwise, the returned value depends upon role_control.cc1. 31. an event change on this register cause an alertl.i_ccstat interrupt.
www. onsemi.com 41 table 43. pwrstat address: 1eh reset value: 08h type: read bit # name r/w/c size (bits) power status description (note 32) 7 debug_acc r 1 debug accessory attached 0b: no debug accessory connected 1b: debug accessory connected reflects the state of the debug_acc output if present 6 tcpc_init r 1 FUSB307B initialization status 0b: the FUSB307B has completed initialization and all registers are valid 1b: the FUSB307B is still performing internal initialization. registers 00?0fh are valid 5 source_hv r 1 sourcing high voltage. see transition flow charts for details. 0b: vsafe5v 1b: high voltage 4 source_vbus r 1 sourcing vbus. output src asserted. 0b: sourcing vbus is disabled 1b: sourcing vbus is enabled 3 vbus_val_en r 1 vbus_val (below) detection circuit status 0b: vbus_val detection is disabled 1b: vbus_val detection is enabled 2 vbus_val r 1 v bus present 0b: v bus disconnected (below 3.5 v) 1b: v bus connected (above 4.0 v) 1 vconn_val r 1 v conn present 0b: v conn is not present or pwrctrl.en_vconn is disabled 1b: this bit is asserted when v conn is present on cc1 or cc2 threshold is fixed at 2.4 v 0 snkvbus r 1 sink vbus. output snk asserted. 0b: sink is disconnected or not supported 1b: FUSB307B has enabled the sink path 32. an event change on this register cause an alertl.i_pwrstat interrupt. table 44. faultstat address: 1fh reset value: 0x80 type: read/write 1 to clear bit # name r/w/c size (bits) fault status interrupt description (note 33) 7 all_regs_reset note r/wc 1 0b: no reset occurred 1b: por or unexpected power reset occurred this bit is asserted when the tcpc resets all registers to their de- fault value. this happens at initial power up or if an unexpected power reset occurs 6 reserved r 1 reserved: 0b 5 auto_disch_fail (note 34) r/wc 1 0b: no discharge failure 1b: vbus discharge failed asserts when pwrctrl.auto_disch is set and FUSB307B fails to discharge vbus to vsafe5v (max.) within tsafe5v or vsafe0v(max.) within tsafe0v from disconnection is detected 4 force_disch_fail r/wc 1 0b: no discharge failure 1b: vbus discharge failed 3 reserved r 1 reserved: 0b 2 reserved r 1 reserved: 0b
www. onsemi.com 42 table 44. faultstat (continued) address: 1fh reset value: 0x80 type: read/write 1 to clear bit # fault status interrupt description (note 33) size (bits) r/w/c name 1 vconn_ocp r/wc 1 0b: no vconn over?current detected 1b: over current on vconn latched. see vconn_ registers to set vconn ocp levels. 0 i2c_error r/wc 1 0b: no error 1b: i2c error has occurred asserts when: or sink_transmit has been sent with transmit_buffer empty (txbytecnt < 2). command.disablevbusdetect is issued while sinking or sourcing vbus.command.sinkvbus is issued while sourcing vbuscommand.sourcevbusdefaultvoltage is issued while sinking vbus command.sourcevbushighvoltage is issued when device is not already sourcing 5 v, is sinking, or is not capable of sourcing high voltage connect_invalid state is reached 33. fault status are latched and cleared when a 1 is written to the corresponding bit. 34. all_regs_reset do not get set on sw_rst.
www. onsemi.com 43 table 45. command address: 23h reset value: 0x00 type: read/write (auto?clear) bit # name r/w/c size (bits) register settings command description 7:0 command r/w 8 0001 0001b wakei2c (no action is taken other than to wake the i2c interface) 0010 0010b disablevbusdetect. disable vbus present detection: pwrstat.vbus_val. the FUSB307B will ignore this command and assert the faultstat.i2c_err if it has sourcing or sinking power over vbus enabled 0011 0011b enablevbusdetect. enable vbus present detection 0100 0100b disablesinkvbus. disable sinking power over vbus. this command does not disable pwrstat.vbus_val detection 0101 0101b sinkvbus. enable sinking power over vbus and enable vbus present detection. the FUSB307B will ignore this command and assert the faultstat.i2c_err if it has sourcing power over vbus enabled 0110 0110b disablesourcevbus. disable sourcing power over vbus. this command does not disable pwrstat.vbus_val detection 0111 0111b sourcevbusdefaultvoltage. enable sourcing vsafe5v over vbus and enable vbus present detection. source shall transition to vsafe5v if at a high voltage. the FUSB307B will ignore this command and assert the faultstat.i2c_err if it has sinking power over vbus enabled 1000 1000b sourcevbushighvoltage. execute sourcing high voltage over vbus. FUSB307B will ignore this command and assert the faultstat.i2c_err 1001 1001b look4con. start drp toggling if rolectrl.drp = 1b. if rolectrl.cc1/cc2 = 01b start with rp, if rolectrl.cc1/cc2 =10b start with rd. if role_control.cc1/cc2 are not either 01b/01b or 10b/10b, then do not start toggling. the tcpm shall issue . command.lok4con to enable the device to restart connection detection in cases where the rolectrl contents will not change. an example of this is when a potential connection as a source occurred but was further debounced by the tcpm to find the sink disconnected. in this case a source only or drp should go back to its unattached.src state. this would result in rolectrl staying the same 1010 1010b rxonemore. configure the receiver to automatically clear the rxdetect register after sending the next goodcrc. this is used to shutdown reception of packets at a known point regardless of packet separation or the depth of the receive fifo in the device 1100 1100b 1101 1101b 1110 1110b reserved. no action 1111 1111b i2cidle, enter i2c idle
www. onsemi.com 44 table 46. devcap1l address: 24h reset value: FUSB307B: ddh type: read bit # name r/w/c size (bits) device capabilities 1 l description 7:5 roles_support r 3 roles supported: 000b: type?c port manager can configure the port as source only or sink only (not drp) 001b: source only 010b: sink only 011b: sink with accessory support 100b: drp only 101b: source, sink, drp, adapter/cable all supported 110b: source, sink, drp 110..111b: not valid 4 sop_support r 1 0b: all sop* except sop?_dbg/sop?_dbg 1b: all sop* messages are supported 3 switch_vconn r 1 supply vconn: 0b: not capable of switching vconn 1b: capable of switching vconn support for pwrstat.vconn_val and pwrctrl.en_vconn implemented 2 snk_vbus r 1 sink vbus: 0b: not capable of controlling the sink path to the system load 1b: capable of controlling the sink path to the system load support for pwrstat.snkvbus and command.sinkvbus imple- mented 1 src_hv r 1 source higher than vsafe5v on vbus 0b: not capable of controlling high voltage path on vbus 1b: capable of controlling high voltage path on vbus support for pwrstat.source_hv and command.sourcevbushighvoltage implemented 0 src_vbus r 1 source vsafe5v on vbus 0b: not of controlling the source path to vbus 1b: capable of controlling the source path to vbus support for pwrstat.source_vbus, command.sourcevbusdefaultvoltage, command.disablesourcevbus, command.enablevbusdetect, and command.disablevbusdetect implemented table 47. devcap1h address: 25h reset value: 0x1e type: read bit # name r/w/c size (bits) device capabilities 1 h description 7:5 reserved r 3 reserved : 000b 4 bleed_dis r 1 0b: no bleed discharge 1b: bleed discharge implement support for pwrctrl.en_bleed_disch implemented. 3 force_dis r 1 0b: no force discharge 1b: force discharge implement support for pwrctrl.force_disch, faultstat.force_disch_fail, and vbus_stop_discl implemented
www. onsemi.com 45 table 47. devcap1h (continued) address: 25h reset value: 0x1e type: read bit # device capabilities 1 h description size (bits) r/w/c name 2 vbus_meas_alrm r 1 0b: no v bus voltage measurement or vbus alarms 1b: v bus voltage measurement and vbus alarms support for vbus_voltage_l, valarmhcfgl and valarmlcfgl implemented 1:0 rp_support r 2 source power supported: 00b: rp default only 01b: rp 1.5 a and default 10b: rp 3.0a, 1.5 a and default 11b: reserved table 48. devcap2l address: 26h reset value: 0xd7 type: read bit # name r/w/c size (bits) device capabilities 2 l description 7 snk_disc_detect r 1 0b: vbus_snk_discl not implemented 1b: vbus_snk_discl implemented 6 stop_dsich r 1 0b: vbus_stop_discl not implemented 1b: vbus_stop_discl implemented 5:4 vbus_alrm_lsb r 2 vbus voltage alarm lsb support 01b: voltage alarm supports 50 mv lsb bit 0 of valarmhcfgl and valarmlcfgl are ignored 3:1 vconn_power_cap r 3 vconn power supported 000b: 1.0 w 001b: 1.5 w 010b: 2.0 w 011b: 3 w (at vconn = 5.5 v) 100b: 4 w 101b: w 110b: 6 w 111b: external 0 vconn_fault_cap r 1 vconn ocp fault capable 110b: FUSB307B is not capable of detecting a vconn fault 1b: FUSB307B is capable of detecting a vconn fault table 49. devcap2h address: 27h reset value: 0x01 type: read bit # name r/w/c size (bits) device capabilities 2 h description 7:1 reserved r 7 reserved: 000_0000b 0 watchdog timer r 1 1b: watchdog timer implemented
www. onsemi.com 46 table 50. std_out_cap address: 29h reset value: FUSB307B: 0x41 type: read bit # name r/w/c size (bits) standard outputs capabilities description 7 reserved r 1 reserved: 00b 6 debug_acc r 1 0b: debug accessory indicator not present 1b: debug accessory indicator present 5 vbus_mon r 1 0b: vbus present monitor not present 4 audio_acc r 1 0b: audio adapter accessory indicator not present 3 active_cable r 1 0b: active cable indicator not present 2 mux_ctrl r 1 0b: mux control not present 1 con_present r 1 0b: connection present indicator not implemented 0 orient r 1 1b: connector orientation present table 51. msgheadr address: 2eh reset value: 0x02 for FUSB307B type: read/write bit # name r/w/c size (bits) message header info description 7:5 reserved r 3 reserved: 000b 4 cbl_plug r/w 1 cable plug 0b: message originated from source, sink, or drp 1b: message originated from a cable plug 3 data_role r/w 1 data role 0b: sink 1b: source 2:1 usbpd_rev r/w 2 usb?pd specification revision 00b: revision 1.0 01b: revision 2.0 10b ? 11b: reserved 0 power_role r/w 1 power role 0b: sink 1b: source table 52. rxdetect rxdetect enables the types of messages and/or signaling to be detected. sop* enabling also turns on auto?goodcrc response. this register is reset when: a hard reset is received or sent; after the goodcrc transmission due to rxonemore; on a disconnect detection; sw_rst or por. address: 2fh reset value: 0x00 type: read/write bit # name r/w/c size (bits) receive detect description (note 35) 7 reserved r 1 reserved: 0b 6 en_cable_rst r 1 0b: do not detect cable reset signaling 5 en_hrd_rst r/w 1 0b: do not detect hard reset signaling (default) 1b: detect hard reset signaling 4 en_sop2_dbg r/w 1 0b: do not detect sop_dbg? message (default) 1b: detect sop_dbg? message 3 en_sop1_dbg r/w 1 0b: do not detect sop_dbg? message (default) 1b: detect sop_dbg? message
www. onsemi.com 47 table 52. rxdetect (continued) rxdetect enables the types of messages and/or signaling to be detected. sop* enabling also turns on auto?goodcrc response. this register is reset when: a hard reset is received or sent; after the goodcrc transmission due to rxonemore; on a disconnect detection; sw_rst or por. address: 2fh reset value: 0x00 type: read/write bit # receive detect description (note 35) size (bits) r/w/c name 2 en_sop2 r/w 1 0b: do not detect sop? message (default) 1b: detect sop? message 1 en_sop1 r/w 1 0b: do not detect sop? message (default) 1b: detect sop? message 0 en_sop r/w 1 0b: do not detect sop message (default) 1b: detect sop message 35. writing all 0s to this register disables pd. table 53. rxbytecnt address: 30h reset value: 0x00 type: read bit # name r/w/c size (bits) received byte count description 7:0 rxbytecnt r 8 number of bytes received. this is the number of bytes in rxdata plus 3 (rxstat and rxheadl, h) table 54. rxstat this register indicates the status of the received sop* message in rxheadl,rxheadh, and rxdata registers. address: 31h reset value: 0x00 type: read bit # name r/w/c size (bits) receive status description 7:3 reserved r 5 reserved: 00000b 2:0 rxsop r 3 received sop 000b: received sop 001b: received sop? 010b: received sop?? 011b: received sop?_dbg 100b: received sop?_dbg 110b: received cable reset all others are reserved. table 55. rxheadl received header low byte is stored here. expected goodcrc messages are not stored. address: 32h reset value: 0x00 type: read bit # name r/w/c size (bits) receive header low description 7:0 rxheadl r 8 rx header data low
www. onsemi.com 48 table 56. rxheadh received header high byte is stored here. expected goodcrc messages are not stored. address: 33h reset value: 0x00 type: read bit # name r/w/c size (bits) receive header high description 7:0 rxheadh r 8 rx header data high table 57. rxdata address: 34h?4fh reset value: 0x00 type: read byte # name r/w/c size (bits) receive payload description 27:0 rxdata0..27 r 8 rx payload table 58. transmit writing this register will start a pd transmission. if cable reset, hard reset or bist carrier mode 2 is written, retry_cnt is ignored and signaling is not retried. address: 50h reset value: 0x00 type: read/write bit # name r/w/c size (bits) transmit description 7:6 reserved r 2 reserved: 00b 5:4 retry_cnt r/w 2 retry counter 00b: no message retry is required 01b: automatically retry message transmission once 10b: automatically retry message transmission twice 11b: automatically retry message transmission three times 3 reserved r 1 reserved: 0b 2:0 txsop r/w 3 transmit sop message 000b: transmit sop 001b: transmit sop? 010b: transmit sop?? 011b: transmit sop_dbg? 100b: transmit sop_dbg? 101b: transmit hard reset 110b: transmit cable reset 111b: transmit bist carrier mode 2 (enabled for tbistcontmode ) table 59. txbytecnt address: 51h reset value: 0x00 type: read/write bit # name r/w/c size (bits) transmit byte count description 7:0 txbytecnt r/w 8 number of bytes to be transmitted table 60. txheadl address: 52h reset value: 0x00 type: read/write bit # name r/w/c size (bits) transmit header low description 7:0 txheadl r/w 8 transmit header low
www. onsemi.com 49 table 61. txheadh address: 53h reset value: 0x00 type: read/write bit # name r/w/c size (bits) transmit header high description 7:0 txheadh r/w 8 transmit header high table 62. txdata addresses: 54?6fh reset value: 0x00 type: read/write byte # name r/w/c size (bits) transmit payload description 27:0 txdata0..27 r/w 8 tx payload table 63. vbus_voltage_l address: 70h reset value: 0x00 type: read bit # name r/w/c size (bits) vbus voltage low description (note 36) 7 vbus_v_bit7 r 1 bit 7 of vbus measurement 6 vbus_v_bit6 r 1 bit 6 of vbus measurement 5 vbus_v_bit5 r 1 bit 5 of vbus measurement 4 vbus_v_bit4 r 1 bit 4 of vbus measurement 3 vbus_v_bit3 r 1 bit 3 of vbus measurement 2 vbus_v_bit2 r 1 bit 2 of vbus measurement 1 vbus_v_bit1 r 1 bit 1 of vbus measurement 0 vbus_v_bit0 r 1 bit 0 of vbus measurement 36. tcpm must read vbus_voltage_l before reading vbus_voltage_h to guarantee adc output and i 2 c are properly synchronized.
www. onsemi.com 50 table 64. vbus_voltage_h address: 71h reset value: 0x00 type: read bit # name r/w/c size (bits) vbus voltage high description (note 37) 7:4 reserved r 4 reserved: 0000b 3:2 vbus_scale r 2 00b: vbus measurement not scaled 01b: vbus measurement divided by 2 10b: vbus measurement divided by 4 11b: reserved 1 vbus_v_bit9 r 1 bit 9 of vbus measurement 0 vbus_v_bit8 r 1 bit 8 of vbus measurement 37. vbus_v_bit[9:0] is the measured vbus voltage divided by vbus_scale factor. table 65. vbus_snk_discl address: 72h reset value: 0xa0 (< vsafe5v: 4.0 v) type: read/write bit # name r/w/c size (bits) vbus sink disconnect threshold low (note 36) 7:0 vbus_snk_disc r/w 8 bits 7:0 of sink disconnect threshold 38. accuracy is set for 50 mv lsb and bit 0 is ignored. table 66. vbus_snk_disch address: 73h reset value: 0x00 type: read/write bit # name r/w/c size (bits) vbus sink disconnect threshold high 7:2 reserved r 6 reserved: 000000b 1:0 vbus_snk_disc r/w 2 bits 9:8 of sink disconnect threshold table 67. vbus_stop_discl address: 74h reset value: 0x1c (< vsafe0v: 700 mv) type: read/write bit # name r/w/c size (bits) vbus stop discharge threshold low (note 39) 7:0 vbus_vth_lo r/w 8 bits 7:0 of stop discharge threshold 39. accuracy is set for 50 mv lsb and bit 0 is ignored. table 68. vbus_stop_disch address: 75h reset value: 0x00 type: read/write bit # name r/w/c size (bits) vbus stop discharge threshold high 7:2 reserved r 6 reserved: 000000b 1:0 vbus_vth_lo r/w 2 bits 9:8 of stop discharge threshold
www. onsemi.com 51 table 69. valarmhcfgl address: 76h reset value: 0x00 type: read/write bit # name r/w/c size (bits) voltage alarm high trip point configuration low description (note 40) 7:0 vbus_vth_hi r/w 8 bits 7:0 of high trip point alarm 40. accuracy is set for 50 mv lsb and bit 0 is ignored. table 70. valarmhcfgh address: 77h reset value: 0x00 type: read/write bit # name r/w/c size (bits) voltage alarm high trip point configuration high description 7:2 reserved r 6 reserved: 000000b 1:0 vbus_vth_hi r/w 2 bits 9:8 of high trip point alarm table 71. valarmlcfgl address: 78h reset value: 0x00 type: read/write bit # name r/w/c size (bits) voltage alarm low trip point configuration low description (note 41) 7:0 vbus_vth_lo r/w 8 bits 7:0 of low trip point alarm 41. accuracy is set for 50 mv lsb and bit 0 is ignored. table 72. valarmlcfgh address: 79h reset value: 0x00 type: read/write bit # name r/w/c size (bits) voltage alarm low trip point configuration high description 7:2 reserved r 6 reserved: 000000b 1:0 vbus_vth_lo r/w 2 bits 9:8 of low trip point alarm
www. onsemi.com 52 table 73. vconn_ocp address: a0h reset value: 0x0f type: read/write bit # name r/w/c size (bits) vconn current limit description (note 42) 7:4 r 4 reserved: 0b 3 ocp_range r/w 1 0b: ocp range between 10 ma ? 80 ma (max_range = 80 ma) 1b: ocp range between 100 ma ? 800 ma (max_range = 800 ma) 2:0 ocp_cur r/w 3 000b: max_range/8 001b: 2 max_range/8 010b: 3 max_range/8 011b: 4 max_range/8 100b: 5 max_range/8 101b: 6 max_range/8 110b: 7 max_range/8 111b: max_range (see ocp_range definition above) 42. only used if vconn_ocp register pwrctrl.en_vconn is set to 1. table 74. reset address: a2h reset value: 0x00 type: readw/write (self clearing) bit # name r/w/c size (bits) reset description 7:2 reserved r 6 reserved:000000b 1 pd_rst r/w 1 0b: no action 1b: reset pd?phy and pd?fsms 0 sw_rst r/w 1 0b: no action 1b: reset all registers to default table 75. gpio1_cfg address: a4h reset value: 0x00 type: read/write bit # name r/w/c size (bits) general purpose i/o 1 configuration 7:3 reserved r 5 reserved:00000b 2 gpo1_val r/w 1 if gpo1_en = 1 0b: set output = 0 1b: set output = 1 1 gpi1_en r/w 1 0b: input buffer disabled 1b: input buffer enabled (input state can be read in gpio_stat register) 0 gpo1_en r/w 1 0b: gpo is high?z 1b: gpo is enabled
www. onsemi.com 53 table 76. gpio2_cfg address: a5h reset value: 0x00 type: read/write bit # name r/w/c size (bits) general purpose i/o 2 configuration 7:4 reserved r 4 reserved:0000b 3 fr_swap_fn r/w 1 enable fast role swap i/o function for gpio2 0b: fr_swap i/o function disabled 1b: fr_swap i/o function enabled 2 gpo2_val r/w 1 generic gpio function if gpo2_en = 1 & fr_swap_fn = 0 0b: set output = 0 1b: set output = 1 initial hub sink fast role swap function if gpo2_en = 1 & fr_swap_fn = 1, set gpo2_val = 1. when a vbus disconnect is detected, the gpio2 pin is automatically set low 1 gpi2_en r/w 1 generic gpio function if fr_swap_fn = 0 0b: input buffer disabled 1b: input buffer enabled (input state can be read in gpio_stat register) initial hub source fast role swap function if fr_swap_fn = 1 & gpo2_en = 0 0b: input buffer disabled 1b: monitor input for a high to low transition and initiate the fast role swap within ttcpcsendfrswap 0 gpo2_en r/w 1 0b: gpo is high?z 1b: gpo is enabled table 77. gpio_stat address: a6h reset value: 0x00 type: read bit # name r/w/c size (bits) general purpose i/o input status 7:2 reserved r 6 reserved: 000000b 1 gpi2_val r 1 if gpi2_en 0b: gpio2 input is low 1b: gpio2 input is high 0 gpi1_val r 1 if gpi1_en 0b: gpio1 input is low 1b: gpio1 input is high table 78. drptoggle address: a7h reset value: 0x00 type: read/write bit # name r/w/c size (bits) drp toggle timing 7:3 reserved r 6 reserved:00000b 1:0 drptoggle r/w 2 00b: ttogglesrc = 15 ms to 30 ms; ttogglesnk = 35 ms to 70 ms 01b: ttogglesrc = 20 ms to 40 ms; ttogglesnk = 30 ms to 60 ms 10b: ttogglesrc = 25 ms to 50 ms; ttogglesnk = 25 ms to 50 ms 11b: ttogglesrc = 30 ms to 60 ms; ttogglesnk = 20 ms to 40 ms
www. onsemi.com 54 table 79. sink_transmit writing this register as a sink will start a pd transmission when the source rp has transitioned from 1.5 a to 3.0 a. if cable reset, hard reset or bist carrier mode 2 is written, retry_cnt is ignored and signaling is not retried. after initial message transmission, the tcpm will monitor ccstat for changes in rp. writing to this register as a source is not allowed. address: b0h reset value: 0x40 type: read/write bit # name r/w/c size (bits) sink transmit description 7 reserved r 1 reserved: 0b 6 dis_snk_tx r/w 1 0b: sink transmit is enabled 1b: sink transmit is disabled 5:4 retry_cnt r/w 2 retry counter 00b: no message retry is required 01b: automatically retry message transmission once 10b: automatically retry message transmission twice 11b: automatically retry message transmission three times 3 reserved r 1 reserved: 0b 2:0 txsop r/w 3 transmit sop message 000b: transmit sop 001b: transmit sop? 010b: transmit sop?? 011b: transmit sop_dbg? 100b: transmit sop_dbg? 101b: transmit hard reset 110b: transmit cable reset 111b: transmit bist carrier mode 2 (enabled for tbistcontmode ) table 80. src_frswap address: b1h reset value: 0x00 type: read/write bit # name r/w/c size (bits) source fast role swap 7:4 reserved r 4 reserved:0000b 3:2 frswap_snk_delay r/w 2 if manual_snk_en is set to 0, enable snk gate after delay below: 00: 0 s (same time fr_swap bit is set). 01: 150 s (after fr_swap signaling is complete) 10: 300 s 11: 600 s 1 manual_snk_en r/w 1 0b: automatic snk enable according to frswap_snk_delay 1b: snk enabled by tcpm 0 fr_swap (note 43) r/wc 1 0b: no action 1b: initiates fast role swap process 43. auto?clear. table 81. snk_frswap address: b2h reset value: 0x00 type: read/write (auto?clear on detect) bit # name r/w/c size (bits) sink fast role swap 7:1 reserved r 7 reserved:000000b 0 en_frswap_dtct (note 44) r/wc 1 0b: no action 1b: enables fast role swap detection 44. auto?clear on detect.
www. onsemi.com 55 table 82. alert_vd address: b3h reset value: 0x00 type: read/write 1 to clear bit # name r/w/c size (bits) vendor defined alert 7 reserved r 1 reserved: 0b 6 i_disch_succ r/wc 1 0b: no interrupt 1b: auto discharge or force discharge successful 5 i_gpi2 r/wc 1 0b: no interrupt 1b: input gpi2 change occurred 4 i_gpi1 r/wc 1 0b: no interrupt 1b: input gpi1 change occurred 3 i_vdd_dtct r/wc 1 0b: no interrupt 1b: vdd detection change occurred (read vd_stat) 2 i_otp r/wc 1 0b: no interrupt 1b: otp condition occurred 1 i_swap_tx r/wc 1 0b: no interrupt 1b: fast role swap sent due to gpio input set low 0 i_swap_rx r/wc 1 0b: no interrupt 1b: fast role swap request received table 83. alert_vd_msk address: b4h reset value: 0x7f type: read/write bit # name r/w/c size (bits) vendor defined alert masks 7 reserved r 1 reserved:0b 6 m_disch_succ r/w 1 0b: interrupt masked 1b: interrupt unmasked 5 m_gpi2 r/w 1 0b: interrupt masked 1b: interrupt unmasked 4 m_gpi1 r/w 1 0b: interrupt masked 1b: interrupt unmasked 3 m_vdd_dtct r/w 1 0b: interrupt masked 1b: interrupt unmasked 2 m_otp r/w 1 0b: interrupt masked 1b: interrupt unmasked 1 m_swap_tx r/w 1 0b: interrupt masked 1b: interrupt unmasked 0 m_swap_rx r/w 1 0b: interrupt masked 1b: interrupt unmasked
www. onsemi.com 56 package dimensions wqfn16 3 x 3, 0.5p case 510bs issue o
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